I build software and the hardware underneath it.

Not really an inventory system. A custody ledger. Its job is to prove who accepted responsibility for a machine, so every transfer captures two signatures on a pad, the employee's and an authority's, and assignment rows are closed rather than deleted. Everything that carries custody history is on_delete=PROTECT: you cannot delete an employee who has ever signed for equipment.

The write-up covers the schema, the write path, a uniqueness constraint I got wrong and why, the backup and restore commands, and the two decisions I would reverse.

Forecasts how much of each menu item a given branch will sell, so inventory can be ordered against a number rather than a hunch, and less food gets thrown away.

The feature pipeline is where most of the thinking went: cyclical encoding for time-of-week and seasonality, 7/14/30-day moving averages, lag features and rolling statistics. Three regression models get trained on that, and whichever has the best 5-fold cross-validated R² is serialised with joblib and used for live predictions. Interface runs in Arabic and English with right-to-left handling.

An ESP32 plugged into a car's OBD-II port, reading live engine parameters. The point is that it doesn't just display them: a rule engine watches for dangerous combinations, readings that are each individually fine but together mean something is wrong, and raises an LED and a buzzer.

Three FreeRTOS tasks share the chip, and the priorities are the design. The OBD reader runs every 100 ms at high priority, because a dropped frame is data you cannot get back. The fault detector runs every 200 ms at medium. The web server sits at the bottom, event-driven, because a dashboard that lags by a second costs nothing. A page served out of LittleFS shows the live values.

AES encryption and decryption built as an explicit algorithmic state machine rather than leaving the control path to be inferred by the synthesiser. The round counter, the register enables and the branch conditions ( isRound0, isRound9, isRound10, count_lt_10) are all written out, with separate datapaths for encryption and decryption covering byte substitution, shift rows, mix columns and their inverses.

Six people outside the course have starred it and four have forked it, which is the only external validation I have on any of this.

A 32-bit RISC processor built once as a single-cycle machine and then again with a pipeline. Datapath, control unit, ALU and register file wired component by component.

It is validated by assembling a selection sort and running it on the machine until it halts with the array in order. If any instruction in the path, the memory interface or a single control signal is wrong, the array comes back scrambled.

This is the project I point at when someone asks whether I understand what is underneath the code I write.